In the semiconductor industry, there is a trend towards fabricating chips with both higher device density and more complex chip functions. Accordingly, the size of semiconductor devices has been greatly reduced. One of the problems caused by this size reduction is that the width of the contact openings between the device or doped regions of a substrate and the overlying conducting layer has been decreased. Narrow contact openings have a relatively large resistance to current, which makes it more difficult to form reliable electrical contacts between the doped regions and the conducting layer, thereby making it more difficult to fabricate reliable semiconductor chips.
The process of forming electrical contacts in a semiconductor device involves etching a dielectric layer overlying the doped regions of a substrate to form contact holes through the dielectric layer and thus expose a portion of each doped region. The dielectric layer is then covered with a conducting layer, such as aluminum, to electrically contact the doped regions through the contact holes. In order to reliably contact these doped regions, the conducting layer is typically sputtered over the dielectric layer and the contact holes. Narrow contact openings, however, result in smaller contact hole areas, thus creating vertical sidewalls in the contact holes. The vertical sidewalls of contact holes generate poor step coverage of the conducting layer because the metal thickness in the contact holes is generally greater than the metal thickness on the top of the dielectric layer. This causes higher contact resistance or even an open circuit between the conducting layer and the doped regions of the substrate.
The above problems have been addressed by filling the contact holes with conducting or plug materials, such as tungsten. This "planarization" of the contact region has been disclosed in U.S. Pat. Nos. 4,884,123 and 4,994,410, the complete disclosure of which is incorporated herein by reference. The manufacturing steps for a typical process utilizing tungsten plug materials are depicted in FIGS. 1A-1E.
Referring to FIG. 1A, a doped region 12, either N-type or P-type, is formed in a silicon substrate 10 by diffusion, which forms a metallurgical junction with substrate 10. An insulating layer 14 comprising an oxide; e.g., nitride or the like, is formed over substrate 10. A contact hole 15 is then formed by chemically etching a patterned opening through insulating layer 14. A layer of titanium 16 is deposited over the surface of insulating layer 14 so that titanium layer 16 extends into contact hole 15 to contact the exposed portion of doped region 12. A titanium-tungsten layer 18 is deposited over titanium layer 16 as a barrier layer.
Referring next to FIG. 1B, the structure of FIG. 1A is then subjected to heating in a nitrogen atmosphere to cause both the formation of a titanium silicide layer 13 at the titanium-silicon interface and the formation of a titanium nitride layer 17 at the interface of the titanium-tungsten and titanium layers 18, 16. Note that the titanium nitride and titanium-tungsten layers both function as a barrier.
Turning to FIG. 1C, after the thermal process, a thick blanket layer of tungsten is deposited over the titanium-tungsten layer 18. The tungsten layer is thick enough to completely fill opening 15. All of the tungsten layer deposited over insulating layer 14 is then substantially removed by an etching process to leave only tungsten plug 19 filled in contact hole 15. Tungsten plug 19 planarizes the contact hole, thereby providing the electrical connection between the doped region and the conducting layer.
Referring to FIG. 1D, a layer of aluminum 20 is applied to the surface of the structure by sputtering to contact tungsten plug 19. Note that aluminum layer 19 does not contact doped region 12 directly, but is electrically connected to doped region 12 through tungsten plug 19, barrier layers 16, 17 and 18 and titanium silicide layer 13.
One drawback with the above process is that the deposition and etching of the tungsten layer increases both the process complexity and the manufacturing cost. In order to form and then etch the tungsten layer, more steps must be added to the manufacturing process, and these extra steps are not consistent with the conventional process of fabricating semiconductor devices. For example, the etching process of a tungsten layer is typically performed by plasma etching using SF.sub.6 or CBrF.sub.3 gases, which requires additional instruments to perform the etching work. These additional instruments are expensive and the extra process steps are not easy to control.